1. Field
An embodiment of the present invention relates to the field of integrated circuit design and, more particularly, to the design of integrated circuits including scan cells.
2. Discussion of Related Art
A typical design process for an integrated circuit begins with architecture design followed by a logic design phase that produces a register transfer level (RTL) model of the integrated circuit and a circuit design phase that produces a switch level schematic. Once a switch level schematic is available, a formal verification (FV) process may be performed to verify that the schematic and the RTL model are functionally equivalent (verify the schematic against the RTL).
While an FV process may be used to verify the schematic against the RTL model for a normal operating mode of the integrated circuit, if scan cells are included in the design, there may be issues during scan operations that were not revealed during FV. Vectors shifted into scan cells through the scan chains included in the integrated circuit may cause contention that is not detected by the FV process, for example.
FIG. 1 shows an example of a portion 100 of an integrated circuit to be verified. The circuit 100 includes control lines 105-107 that act as select lines for the multiplexer (mux) 110. The mux 110 receives input values on input lines 111-113 and provides an output at node 115. In this example, during a normal mode of operation, the logic 120 is configured to ensure that only one of the select lines 105-107 is asserted at any one time. During this normal mode of operation, scan cells 126-128 coupled to outputs of the logic 120 act as simple latches that pass output values from the logic 120 through a scan cell fan-out cone 130 to the select lines 105-107 of the mux 110.
By ensuring that only one of the select lines 105-107 is asserted at once, contention is avoided at the output node 115 in the case that different input values are received on the input lines 111-113. Contention at the output node 115 creates a DC current path that can damage a chip that includes the integrated circuit 100 and/or compromise its reliability.
While contention at a mux output node 115 is described above, contention may also occur on a bus with a similar configuration (e.g. a tristate bus), for example, in a similar manner and may be even more problematic.
During an FV process to verify the circuit 100, where FV is performed at sequential logic boundaries, the logic 120 does not control the values of the control signals 105-107 because there is a sequential boundary at the scan chain 125. Thus, one or more FV properties may be specified at the inputs of the logic 130 to constrain the controlling signals 105-107 such that only one of the signals can be asserted at any one time. An example of such a property may be MUTEX (105, 106, 107) (where MUTEX indicates mutually exclusive).
When FV is performed on the circuit 100 using this FV property, contention is avoided at the output node 115 during the FV process.
An issue may arise, however, during scan testing, when test vectors are shifted into the scan chain and/or when they are applied to the signal lines 105, 106 and 107. During such testing, the logic 120 does not have control over the values of the signals applied to the signal lines 105-107. Because any combination of values may be shifted into the scan cells 126-128 during scan testing, contention may be caused at the output node 115 either during a shift operation or as the vector shifted into the scan chain is otherwise applied to the signal lines 105-107.
Currently, such sites where contention may occur during scan testing can be difficult to detect. One approach is to exhaustively simulate all possible test vectors that may be applied to each scan chain. Another approach is to inspect contention sites manually after an issue, such as wafer or circuit damage, has occurred. Such processes are time consuming, may require additional expertise, may be subject to human error and/or may happen late in the manufacturing cycle such that any design changes are expensive to make.
Where immediate damage to a chip does not occur as a result of contention, or the circumstances that cause the contention are relatively rare, some manufacturers may choose to ignore the issue. Quality or reliability of the integrated circuit chip may be compromised as a result.
Another approach is to design scan cells that do not cause contention. This may be done, for example, by avoiding the use of tristate elements. Such a design approach may, however, unacceptably compromise the speed of the integrated circuit. Alternatively, scan cells may be designed to hold their state such that contention issues are avoided during scan shift operations. Some scan cells designed in this manner may result in increased area and operation overhead.